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W29GL128C
7.2.9.2
Chip Erase
The Chip Erase operation returns all memory locations containing a bit state of “0” to the “1” state,
effectively clearing all data. This action requires six instruction cycles to commence the erase
operation. The unlock sequence is the first two cycles, followed by the configuration cycle, the fourth
and fifth are also ”unlock cycles”, and the sixth cycle initiates the chip erase operation.
Once the chip erase algorithm begins, no other instruction will be accepted. However, if a hardware
reset is executed or the operating voltage is below acceptable levels, the chip erase operation will be
terminated and automatically returns to Read mode.
The embedded chip erase algorithm status can be verified by the following:
Status
In progress
Exceeded time limit
DQ7
0
0
DQ6
Toggling
Toggling
DQ5
0
1
DQ2
Toggling
Toggling
RY/#BY 1
0
0
Table 7-5
Note:
Polling During Embedded Chip Erase Operation
1.
7.2.10
RY/#BY is an open drain pin and should be connected to VCC through a high value pull-up resistor.
Erase Suspend/Resume
If there is a sector erase operation in progress, an Erase Suspend instruction is the only valid
instruction that may be issued. Once the Erase Suspend instruction is executed during the 50μs time-
out period following a Sector Erase instruction, the time-out period will terminate right away and the
device will enter Erase-Suspend Read mode. If an Erase Suspend instruction is executed after the
sector erase operation has started, the device will not enter Erase-Suspended Read mode until
approximately 20μs (5μs typical) time has elapsed. To determine the device has entered the Erase-
Suspend Read mode, use DQ6, DQ7 and RY/#BY status to verify the state of the device.
Once the device has entered Erase-Suspended Read mode, it is possible to read or program any
sector(s) except those being erased by the erase operation. Only the contents of the status register is
present when attempting to read a sector that has been scheduled to erase or be programmed when
in the suspend mode. A resume instruction must be executed and recommend checking DQ6 toggle
bit status, before issuing another erase instruction.
The status register bits can be verified to determine the current status of the device:
Status
DQ7
DQ6
DQ5 DQ3 DQ2 DQ1 RY/#BY
Erase suspend read in erase suspended sector
1
No toggle 0
N/A Toggle N/A
1
Erase suspend read in non-erase suspended sector
Data
Data
Data Data Data Data
1
Erase suspend program in non-erase suspended sector DQ7# Toggle
Table 7-6
Polling During Embedded Erase Suspend
0
N/A N/A N/A
0
Instruction sets such as read silicon ID, sector protect verify, program, CFI query and erase resume
can also be executed during Erase-Suspend mode, except sector and chip erase.
7.2.11 Sector Erase Resume
Only in the Erase-Suspended Read mode can the Sector Erase Resume instruction be a valid
command. Once erase resumes, another Erase Suspend instruction can be executed, but allow a
400μs interval between Erase Resume and the next Erase Suspend instruction.
10
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